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ir3548 1 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 60a dual integrated powirstage features ? integrated dual, doubler or quad mode driver ? 2 pairs of high and low side mosfets ? peak efficiency up to 94% at 1.2v ? variable gate drive , vdrv, from 4 .25v to 12 v to optimize system efficiency ? 5v vcc and vdrv capability for sleep states where on ly 5v is available ? input voltage (vin) range of 4.25v to 17 v ? output current capability of 30a/phase ? switching frequency up to 1.5mhz ? ultra - low rg mosfet technology minimizes switching losses for optimized high frequency performance ? synchronous mos fet with monolithic integrated schottky diode reduces dead - time and diode reverse recovery losses ? low quiescent current (1ua typical) for vr12.6/vr12.6+ notebook applications. ? independent enable control for each phase ? support both industry standard 3.3v t ri - state p wm and ir active tri - level (atl) pwm logic ? small 6mm x 8 mm x 0.9mm pqfn package ? lead - free rohs compliant package applications ? high frequency, low profile dc - dc converters ? voltage regulators for cpus, gpus, and ddr memory arrays of servers, notebook. description the ir3548 is a dual integrated powirstage? is a with 2 pairs of co - packed control and synchronous mosfets and an optimized dual phase driver. the package is optimized internally for pcb layout, heat transfer and package inductance. the integ rated drive r is capable of operating as a d ual driver (2 pwm controlling 2 phases ), a d oubler driver (1 pwm controlling 2 phases) or a quad driver (1 pwm controlling 4 phases in two ir3548s ). up to 1.5mhz switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry l eading efficiency. integrating two phases in one package while still providing superior efficiency and thermal performance , the i r3548 enables smallest size and lower solution cost. the lower quiescent current makes it suitable for ne x t generation vr12.6/vr12.6+ notebook applications. the ir3548 uses ir?s latest generation of low voltage mosfet technology characterized by ultra - lo w gate resistance ( rg) and charge (qg) that result in minimized switching losses. the synchronous mosfet optimizes conduction losses and features a monolithic integrated schottky to significantly reduce dead - time and diode conduction and reverse recovery l osses. the ir3548 is optimized specifically for cpu core power delivery in 12vin applications like servers, certain notebooks, gpu and dr memory designs. ordering information base part number package type standard pack orderable part number form quantity ir3548m trpbf pqfn 6 mm x 8 mm tape and reel 3 000
ir3548 2 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 pinout diagram vin1 vin1 vindiv en1 pwm1 vcc boot1 gatel1 lgnd pgnd vdrv gatel2 boot2 pwm2 / pwmio1 en2 / pwmio2 function mode vin2 vin2 vin2 vin2 gatel2 pgnd pgnd sw2 sw1 sw1 sw1 sw1 sw1 sw1 sw1 sw1 sw1 sw2 sw2 sw2 sw2 sw2 sw2 sw2 sw2 sw2 vin1 vin1 pgnd pgnd gatel1 sw1 pgnd figure 1: ir3548 top view
ir3548 3 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 functional block dia gram function sw1 en1 36 37 38 39 40 41 42 43 44 1 2 48 49 vin1 vin1 vin1 vin1 sw1 sw1 sw1 sw1 sw1 sw1 sw1 sw1 13 boot2 7 boot1 power-on reset (por), reference, mode (pwm or ir atl), function (dual, doubler, or quad), and driver dead-time control 4 lgnd 9 vdrv 11 en1 4 driver driver 3 vindiv 17 mode 14 pwm2 / pwmio1 vdrv ir3548 vdrv 35 sw1 q1 q2 sw2 20 21 25 26 27 28 29 30 sw2 sw2 sw2 sw2 sw2 vin2 vin2 31 32 pgnd pgnd driver driver vdrv 19 vin2 q3 q4 18 vin2 33 sw2 sw2 sw2 46 24 gatel2 gatel2 22 12 vcc or vdrv uvlo or t > 150c vcc 6 16 en2 / pwmio2 15 pwm1 5 vin1 lgnd pgnd 50 vin1 14 pgnd 23 47 pgnd 8 gatel1 sw2 pgnd 10 45 gatel1 34 figure 2 : block diagram t able 1: f unction and m ode p in c onfiguration t able pin 16 ? f unction? pin 17 ? m ode? fun ctionality pwm mode pin 4 ?en1? function pin 14 function pin 15 function 0 1 dual ir atl loop 1 pwm2 en2 1 1 doubler ir atl loops 1 & 2 na na float 1 quad master ir atl loops 1 & 2 pwmio1 (output) pwmio2 (output) 0 0 dual tri -state loop 1 pwm2 en2 1 0 doubler tri -state loops 1 & 2 na na float 0 quad slave na loops 1 & 2 pwmio1 (input) pwmio2 (input)
ir3548 4 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 typ ical application sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv v in v out c in2 47uf x4 c boot1 0.22uf l1 150nh c out 470uf x3 c in1 0.1uf x2 5v c vcc 0.1uf sw2 boot2 c boot2 0.22uf l2 150nh vdrv vdrv c vdrv 1uf pwm2 en2 + cs1 - + cs2 - gatel1 gatel2 gatel2 gatel1 vinsen pwm1 psi#1 pwm2 psi#2 ir3588 + cs1 - isen1 irtn1 isen2 irtn2 + cs2 - vrtn vsen vrdy sv_alert# sv_clk sv_dio en sm_dio sm_clk vrhot_icrit# vcc cflt lgnd svaddr_1 addr_prot 3.3v tsen rcsp rcsm c 3v3 1uf c flt 1uf c rcs 100pf d tsen r t 10k c cs1 0.22uf c cs2 0.22uf r cs2 2.49k r cs1 2.49k from / to system figure 3: high density two - phase voltage regulator, standard tri -state pwm, dual driver mode sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv v in v out1 c in2 47uf x4 c boot1 0.22uf l1 150nh c out1 470uf x3 c in1 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot2 0.22uf l2 150nh vdrv vdrv c vdrv 1uf pwm2 en2 v out2 c out2 470uf x3 two single- phase pwm controllers gatel1 gatel1 gatel2 gatel2 c cs1 0.22uf r cs1 2.49k c cs2 0.22uf r cs2 2.49k + cs1 - + cs2 - + cs1 - + cs2 - + - v out1 sense + - v out2 sense figure 4: ir3548 two single - ph ase voltage regulator s, standard tri - state pwm , dual driver mode
ir3548 5 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 sw1 vin1 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv v in v out c in2 47uf x4 c boot1 0.22uf l1 150nh c out1 470uf x3 c in1 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 vdrv vdrv c vdrv 1uf pwm2 en2 single- phase pwm controller gatel1 gatel1 gatel2 gatel2 c cs1 0.22uf r cs1 2.49k + cs1 - + cs1 - + v out sense - figure 5: ir3548 single-phase voltage regulator, standard tri -state pwm, dual driver mode sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv v in v out c in2 47uf x4 c boot1 0.22uf l1 150nh c out1 470uf x3 c in1 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot2 0.22uf l2 150nh vdrv vdrv c vdrv 1uf pwm2 en2 single- phase pwm controller gatel1 gatel1 gatel2 gatel2 r cs1 4.99k c cs 0.22uf r cs2 4.99k + cs12 - + v out sense - v cc + cs12 - figure 6: ir3548 two-phase voltage regulator, standard tri -state pwm, doubler driver mode
ir3548 6 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 pin descriptions pin # pin name pin description 1, 2, 48, 49 vin1 high current input supply pins for phase 1 . recommended operating range is 4. 25v to 17v. connect at least a 10uf 1206 ceramic capacitor and a 0.1uf 0402 ceramic capacitor. place the capacitors as close as possible to vin1 pins and pgnd pins (46 and 47). the 0.1uf 0402 capacitor should be on the sa me side of the pcb as the ir3548 . 3 vindiv output containing divided vin 1 analog information, (vin 1 - lgnd) / 14 with respect to lgnd. the interna l resistor divider is disconnected from vin 1 when en1 is low. 4 en1 phase 1 enable input in dual mode and phases 1 & 2 enabl e input in doubler or quad mode. grounding this pin places phase 1 in low quiescent mode as a dual driver and sets both phases in low quiescent mode as a doubler or quad driver. the pin is also used to communicate vdrv uvlo, vcc uvlo or over temperature condition; en1 is pulsed low under the fault. the pin must be driven high with a pullup resistor or grounded and should not be floate d. 5 pwm1 the pwm1 is the control input for the first driver with eith er an ir atl compatible signal or an industry standard tri-state signal. connect this pin to the pwm output of the controller. as a dual driver, pwm1 controls gate d river s for phase 1 (q1 and q2), and as a doubler or quad driver, pwm1 controls both phases (q1 and q2 as well as q3 and q4 ) . 6 vcc bias voltage for control logic. connect this pin to a +5v bias supply. place a high quality low esr 0.1uf ceramic capacitor from this pin to the lgnd pin. 7 boot1 floating bootstrap supply pin for the gate drive of control mosfet q1 . connect the bootstrap capacitor between this pin and the sw1 pin. the bootstrap capacitor provides the charge to turn on the control mosfet q1 . see the internal bootstrap device section under description for guidance in choosing the capacitor value. 8, 45 gatel1 g ate connection of the phase 1 synchronous mosfet q2 . use a short, wide and direct pcb trace to connect the two pins. 9 lgnd bias and reference ground. all control signals are referenced to this node. 10, 23, 24, 46, 47 , 50 pgnd high current power g round. note all pins are internally connected in the package. provide low resistance connections to the ground plane and respective output capacitors. 11 vdrv connect this pin to a separate supply voltage between 4.25v and 12v to vary the drive voltage on both the control and synchronous mosfets. place a high quality low esr ceramic capacitor from this pin to p gnd pin (10) . 12, 22 gatel2 gate connection of the phase 2 synchronous mosfet q4 . use a short, wide and direct pcb trace to connect the two pins. 13 boot2 floating bootstrap supply pin for the gate dri ve of control mosfet q3 . connect the bootstrap capacitor between this pin and the sw2 pin. the bootstrap capacitor provides the charge to turn on the control mosfet q3 . see the internal bootstrap device section under description for guidance in choosing the capacitor value. 14 pwm2 / pwmio1 dual function pin. it is pwm2 in d ual mode. the pwm2 is the contro l input for the second driver with either an ir atl compatible signal or an industry standard tri-state signal. connect this pin to the pwm output of the controller. as a dual driver, pwm2 controls gate drivers for phase 2. as a doubler driver, the pin is un-used and is internally disconnected. as a quad driver, the pin becomes pwmio1, a cmos input or output depending on the configuration of the ir3548 as a slave or master repectively. refer to table 1 on page 3 for more details. 15 en2 / pwmio2 dual functi on pin. it is phase 2 enable input as a dual driver . the pin must be driven high or low in this mode and should not be floated. grounding this pin places phase 2 in low quiescent mode. as a doubler driver, the pin is un-used and is internally disconnected. as a quad driver, the pin becomes pwmio2, a cmos input or output depending on the configuration of the ir3548 as a slave or master respectively. refer to table 1 on page 3 for more details. 16 function function pin used to select between dual, doubler an d quad driver m odes. voltage lower than 0.8v sets dual mode; voltage higher than 2.0v sets doubler mode; floating the pin (or between 1.2v and 1.6v) sets quad mode. this pin in combination with the mode pin also determines master or slave behavior in quad mode. the pin status is sensed when en1 is enabled or vcc uvlo is cleared. refer to table 1 on page 3 for more details .
ir3548 7 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 pin # pin name pin description 17 mode pwm mode pin used to select either ir atl input or industry tri - state pwm input . this pin in combination with the function pin also determines master or slave behavior in quad mode. pin should be tied to lgnd or vcc, and the pin status is sensed at en1 enable or when vcc uvlo is cleared. refer to table 1 on page 3 for more details . 18-21 vin2 high current input supply pins for phase 2 . recommended operating range is 4. 25v to 17v. connect at least a 10uf 1206 ceramic capacitor and a 0.1uf 0402 ceramic capacitor. place the capacitors as close as possible to vin2 pins and pgnd pins (23 and 24). the 0.1uf 0402 capacitor should be on the sa me side of the pcb as the ir3548 . 25 - 34 sw2 high current switch node for phase 2 (q3 and q4) . 35 - 44 sw1 high current switch node for phase 1 (q1 and q2) .
ir3548 8 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 absolute maximum rat ings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. pin number pin name v max v min i source i sink 1, 2, 48, 49 vin1 25v -0.3v 5 a rms 20a rms 3 vindiv vcc +0.3v -0.3v 1ma 1ma 4 en1 vcc +0.3v -0.3v 1ma 50ma 5 pwm1 vcc +0.3v -0.3v 5ma 1ma 6 vcc 6.5v -0.3v na 100ma 7 boot1 15 v with respect to sw1, 35v with respect to pgnd - 0.3v wi th respect to sw1 1a for <100ns, 100ma dc 2a for <100ns, 100ma dc 8, 45 gatel1 15v with respect to pgnd - 5v for <200ns, -0.3v dc with respect to pgnd 2a for <100ns, 200ma dc 4a for <100ns, 200ma dc 9 lgnd 0v 0v 50ma 1ma 10, 23, 24, 46, 47, 50 pgnd 300mv -300mv 40a rms 80a rms 11 vdrv 13.2v -0.3v na 200ma 12, 22 gatel2 15v with respect to pgnd - 5v for <200ns, -0.3v dc with respect to pgnd 2a for 100ns, 200ma dc 4a for <100ns, 200ma dc 13 boot2 15 v with respect to sw2, 35v with respect to pgnd - 0.3v w ith respect to sw2 1a for <100ns, 100ma dc 2a for <100ns, 100ma dc 14 pwm2 / p wmio1 vcc +0.3v -0.3v 10ma 10ma 15 en2 / pwmio2 vcc +0.3v -0.3v 10ma 10ma 16 function vcc +0.3v -0.3v 5ma 1ma 17 mode vcc +0.3v -0.3v 5ma 1ma 18-21 vin2 25v -0.3v 5 a rms 20a rms 25-34 sw2 25v - 8v for <200ns, - 0.3v dc 50 a rms 25a rms 35-44 sw1 25v - 8v for <200ns, - 0.3v dc 50 a rms 25a rms thermal information thermal resistance, junction to top ( jc_top ) 11.0 c/w thermal resistance, junction to pcb (pin 47 ) ( jb ) 1.7 c/w thermal resistance ( ja ) 1 18.4 c/w maximum operating junction temperature -40c to 150c maximum storage temperature range -65c to 150c esd rating hbm class 1a jedec standard msl rating 3 reflow temperature 260c note: 1. thermal resistance ( ja ) is measured with the component mounted on a high effective thermal conductivity test board in free air. refer to international rectifier application note an-994 for details.
ir3548 9 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 electrical specifica tions the electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. recommended operatin g conditions for rel iable operation with margin parameter min symbol max unit recommended vin range 4.25 vin 17 v recommended vcc 4.25 vcc 5.5 v recommended vdrv 4.25 vdrv 12 v recommended switching frequency 200 ? sw 1500 khz recommended operating junction temperature -40 t j 125 c electrical character istics parameter symbol conditions min typ m ax unit efficiency powirstage? peak efficiency note 2 93.8 % bootstrap pfet forward voltage v fwd _pfet i(boost) = 35ma 450 595 950 mv thermal flag rising threshold t rise note 1 150 c falling threshold t fall note 1 130 c pwm input , ir atl mode , figure 8 pwm input high threshold v ih _atl 0.95 1.04 1.12 v pwm input low threshold v il _atl 0.75 0.84 0.93 v pwm tri -level high threshold v th _atl 2.41 2.65 2.79 v pwm tri -level low threshold v tl _atl 2.21 2.45 2.56 v pwm input current low i l_atl v pwm = 0v -130 -100 -65 ua pwm input current mid i m_atl v pwm = 1.8v -840 -600 -360 ua pwm input current high i h_atl v pwm = 2.7v -1.4 -1.0 -0.6 ma minimum recognized pwm pulse width minpwm note 1 50 ns pwm input , tri -state mode (+3.3v or +5v signal level) , figure 7 pwm input rising threshold v ih _pwm 2.41 2.65 2.79 v pwm input falling threshold v il _pwm 0.75 0.84 0.93 v tri -state lo_gate threshold v t l_pwm 0.95 1.04 1.12 v tri -state lo_gate hysteresis v t lh_pwm 200 mv tri -state hi_gate threshold v t h_pwm 2.21 2.45 2.56 v tri - state hi_gat e hysteresis v t hh_pwm 200 mv tri -state hold off time t thold _pwm note 1 80 ns pwm input pull-up voltage v it_p wm pwm input floating 1.40 1.60 1.80 v pwm input resistance r pwm pwm input floating 3.00 3.75 4.50 k? minimum recognized pwm pulse width t pwm_min note 1 30 ns
ir3548 10 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 parameter symbol conditions min typ m ax unit vindiv divider ratio vindiv vindiv / vin 13 14 15 v/v disable vin bias i vin_off 1 a vindiv input resistance r vindiv 540 k? enable inputs (en1, en2) enable1 delay t d_en1 power-on de lay 10 s enable2 delay t d_en2 power-on delay 1 s input high voltage v ih_en 1.15 2.00 2.70 v input low voltage v il_en 0.54 0.80 1.20 v input resistance r en no uvlo or o ver temperature fault @ 5v 450 500 550 k? en1 fault pull down resistance r en_pull_down note 1 100 ohm function and mode input high voltage v ih_func_mode 2 v input low voltage v il_func_mode 0.8 v maximum float pin capacitance c func_mode_max note 1 20 pf pwmio input high voltage v ih _pwmio 2 v input low voltage v il_pwmio 0.8 v output high voltage v oh _pwmio 2.5 5 v output low voltage v ol_pwmio 0 0.5 v supply supply bias current off i v cc_off + i vdrv _off en1=0v 1 5 ua vdrv supply bias current i vdrv f pwm = 400khz, vdrv=5v 30 40 ma vcc supply bias current i vcc_atl atl pwm mode 0.865 2 ma i vcc _pwm tri -state pwm mode 1.13 2 ma vcc rising threshold for por v cc_ rise 3.85 4.20 v vcc falling threshold for por v cc_ fall 3.35 v vdrv rising threshold for por v drv_ rise 3.7 4.20 v vdrv falling threshold for por v drv_ fall 3.28 v notes 1. guaranteed by design but not tested in production 2. v in =12v, v out =1.2v, ? sw = 400kh z, l=150nh (0.29m), vcc= 7 v, c in =47uf x 4, c out =470uf x3, no airflow, no heat sink, 25c ambient temperature, and 8-layer pcb of 3.7? (l) x 2.6? (w). pwm controller loss and inductor loss are not included.
ir3548 11 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 timing diagrams figure 7: ir354 8 timing diagram in standard pwm mode figure 8 : ir3548 timing diagram in international rectifier?s active tri- level ? (atl) pwm mode pwm sw gatel normal pwm tri - state tri - state v ih _ pwm v il _ pwm v it _ pwmi normal pwm gatel pwm normal pwm atl tri-state atl tri-state normal pwm v ih_atl v il_atl v th_atl v tl_atl sw
ir3548 12 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv c in2 47uf x2 c boot1 0.22uf l1 150nh c in1 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot2 0.22uf l2 150nh vdrv vdrv c vdrv 1uf pwm2 en2 + cs1 - + cs2 - gatel1 gatel2 gatel2 gatel1 c cs1 0.22uf c cs2 0.22uf r cs2 2.49k r cs1 2.49k sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv v in v out c in4 47uf x2 c boot3 0.22uf l3 150nh c out 470uf x3 c in3 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot4 0.22uf l4 150nh vdrv vdrv c vdrv 1uf pwm2 en2 + cs3 - + cs4 - gatel1 gatel2 gatel2 gatel1 c cs3 0.22uf c cs4 0.22uf r cs4 2.49k r cs3 2.49k four- phase pwm controller + - v out sense + - cs4 vcc vcc pwm3 sw4 sw3 sw1 sw2 gatel2 gatel1 gatel3 gatel4 pwm1 pwm2 to pwm controller + cs3 - pwm4 en3 en4 en1 en2 + cs1 - + cs2 - pwm3 pwm4 en3 en4 pwm1 pwm2 pwm3 pwm4 sw1 gatel1 sw2 gatel2 sw3 gatel3 sw4 gatel4 figure 9 : timing diagram of the ir3548 four-phase voltage regulator, ir atl pwm, dual driver mode
ir3548 13 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv c in2 47uf x2 c boot1 0.22uf l1 150nh c in1 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot2 0.22uf l2 150nh vdrv vdrv c vdrv 1uf pwm2 en2 gatel1 gatel2 gatel2 gatel1 c cs12 0.22uf r cs2 4.99k r cs1 4.99k sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 vindiv v in v out c in4 47uf x2 c boot3 0.22uf l3 150nh c out 470uf x3 c in3 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot4 0.22uf l4 150nh vdrv vdrv c vdrv 1uf pwm2 en2 + cs34 - gatel1 gatel2 gatel2 gatel1 c cs34 0.22uf r cs4 4.99k r cs3 4.99k two- phase pwm controller + - v out sense + - cs34 vcc vcc pwm2 sw4 sw3 sw1 sw2 gatel2 gatel1 gatel3 gatel4 pwm1 to pwm controller + cs12 - en2 en1 pwm2 en2 + cs12 - pwm1 pwm2 sw1 gatel1 sw3 gatel3 sw2 gatel2 sw4 gatel4 figure 10 : timing d iagram of the ir3548 four- phase voltage regulator, ir atl pwm, doubler driver mode
ir3548 14 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 master vindiv c in2 47uf x2 c boot1 0.22uf l1 150nh c in1 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot2 0.22uf l2 150nh vdrv vdrv c vdrv 1uf pwm2 / pwmio1 en2 / pwmio2 gatel1 gatel2 gatel2 gatel1 c cs12 0.22uf r cs2 10k r cs1 10k sw1 vin1 vin2 pgnd vcc boot1 pwm1 lgnd function en1 mode ir3548 slave vindiv v in v out c in4 47uf x2 c boot3 0.22uf l3 150nh c out 470uf x3 c in3 0.1uf x2 vcc c vcc 0.1uf sw2 boot2 c boot4 0.22uf l4 150nh vdrv vdrv c vdrv 1uf + cs1234 - gatel1 gatel2 gatel2 gatel1 c cs1234 0.22uf r cs4 10k r cs3 10k single- phase pwm controller + - v out sense + - cs1234 vcc sw4 sw3 sw1 sw2 gatel2 gatel1 gatel3 gatel4 pwm1 en1 pwm2 / pwmio1 en2 / pwmio2 pwm1 sw1 gatel1 sw3 gatel3 sw2 gatel2 sw4 gatel4 figure 11 : timing d iagram of the ir3548 four-phase vo ltage regulator, ir atl pwm, quad driver mode
ir3548 15 www.irf.com ? 20 13 international rectifier submit datasheet feedback january 08, 2014 typical operating ch aracteristics circuit of figure 34 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), two phases, dual driver , pwm mode, vcc = 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6? (w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 12: typical ir3548 efficiency figure 1 3: typical ir3548 power loss figure 1 4: normalized power loss vs. input voltage figure 1 5 : normalized power loss vs. output voltage figure 1 6: normalized power loss vs. switching frequency figure 1 7: normalized power loss vs. vdrv voltage 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 0 5 10 15 20 25 30 35 40 45 50 55 60 65 output current (a) efficiency (%) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 5 6 7 8 9 10 11 12 13 14 15 input voltage (v) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 case temperature adjustment (c) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 vdrv voltage (v) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 4.4 5.5 case temperature adjustment (c) 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 output current (a) power loss (w) 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 200 300 400 500 600 700 800 900 1000 switching frequency (khz) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 4.4 5.5 6.6 7.7 8.8 9.9 case temperature adjustment (c) 1.10 1.15 1.20 1.25 1.30 1.35 1.40 power loss 2.2 3.3 4.4 5.5 6.6 7.7 8.8 ure adjustment (c)
ir3548 16 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 typical operating ch aracteristics circuit of figure 34 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), two phases, dual driver, pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 18 normalized power loss vs. output inductor figure 19 thermal derating curve figure 20 vcc current vs. switching frequency figure 21 vdrv current vs. switching frequency figure 22 standard pwm mode, d ual driver , 0a figure 2 3 standard pwm mode, d ual driver, 60a 0 20 40 60 80 100 120 140 160 180 200 300 400 500 600 700 800 900 1000 fsw (khz) vdrv current (ma) vdrv=12v, 2 phases vdrv=7v, 2 phases vdrv=5v, 2 phases vdrv=12v, 1 phase vdrv=7v, 1 phase vdrv=5v, 1 phase pwm1 5v/div sw1 10v/div 1us/div pwm2 5v/div sw2 10v/div 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 120 130 140 150 160 170 180 190 200 210 output inductor (nh) normalized power loss -3.3 -2.2 -1.1 0.0 1.1 2.2 3.3 4.4 5.5 6.6 7.7 case temperature adjustment (c) pwm1 5v/div sw1 10v/div 1us/div pwm2 5v/div sw2 10v/div 0.0 0.5 1.0 1. 5 2. 0 2.5 3.0 200 300 400 500 600 700 800 900 1000 fsw (khz) vcc current (ma) pwm mode, 2 phases pwm mode, 1 phase
ir3548 17 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 typical operating ch aracteristics circuit of figure 34 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), two phases, dual driver, pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 2 4 standard pwm mode, doubler driver , 0a (circuit of figure 6) fig ure 25 pwm to switching delay in pwm mode, 10a figure 26 tristate delays in pwm m ode , 10a figure 27 tristate delays in pwm mode , 10a figure 28 pwm to switching delays in ir atl mode, 10a (circuit if figure 9 ) figure 29 tristate delays in ir atl mode, 10a (circuit of figure 9 ) pwm 2v/div sw 5v/div 100ns/div pwm 2v/div sw 5v/d iv 100ns/div pwm1 2v/div sw1 10v/div 1us/div sw2 10v/div pwm 2v/div sw 5v/div 100ns/div pwm 2v/div sw 5v/div 40ns/div pwm 2v/div sw 5v/div 40ns/div
ir3548 18 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 typical operating ch aracteristics circuit of figure 34 , v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), two phases, dual driver, pwm mode, vcc= 5v, vdrv=7v, t ambient = 25c, no heat sink, no air flow, 8 - layer pcb board of 3.7 ?(l) x 2.6?(w), no pwm controller loss, no inductor loss, unless specified otherwise. figure 30 tristate delays in ir atl mode, 10a (circuit of figure 9 ) figure 31 enable control, 0a figure 32 enable control , 0a figure 3 3 vindiv to vin rati o pwm 2v/div sw 5v/div 40ns/div 13.5 13.6 13.7 13.8 13.9 14.0 14.1 14.2 14.3 14.4 14.5 4 6 8 10 12 14 16 input voltage (v) vindiv ratio en 5v/div sw1 5v/div 2us/div en 5v/div sw1 5v/div
ir3548 19 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 general description the ir3548 contains two high - efficiency and high - speed mosfet drivers optimized to drive two pairs of integrated control and synchronous n- channel mosfets up to 1.5mhz. the ir3548 accepts industry standard 3.3v tri - state pwm signal and is 5v comp liant . it also works with i nternational rectifier?s controller s with active tri - level (atl) pwm output s . the patented ir atl pwm allow s complete enable and disable control of both mosfet pairs through the pwm input signal from the controller. the ir3548 can be configured in three different operating driver modes , dual driver, doubler driver and quad driver so that one pwm signal can con trol one- , two - or four - phase buck converter . the ir 3548 provides two enable inputs to control the two independent phases while operating in dual driver mode, which reduce s quiesecent current to 1 ua (typical) . the ir35 4 8 provides vcc and vdrv under voltag e lockout (uvlo) and over temperature f ault protection, which pulls low e n1 when the fault occurs . the wide range of the vdrv driver voltage from 4.25v to 12v makes it possible to optimize system efficiency for applications with different switching frequencies, input voltages, and output voltages. theory of operation power - on reset (por) the ir3548 incorporates power - on reset protection . this ensures that both the high - and low - side output drivers are active only after the ir3548 supply voltage vcc and v drv both have exceeded a certain minimum operating threshold. the v cc and v drv supp lies are monitored and both drivers are set to the low state, holding both external mosfets off. once vcc and vdrv cross the rising por threshold and if the ir3548 is in ir atl mode, the outputs are held in the off state until a transition from tri - state to active operation is detected at the pwm input. this startup configuration ensures that any undetermined pwm signal levels from a controller in pre - por state will not resu lt in control mosfet or synchronous mosfet turn on until the controller is out of its por. for tri - state pwm mode, the por operation is the same except that the driver does not look for an input tri - state before functioning . during normal operation the drivers continue to remain active until vcc or vdrv fall below their respective falling por thresholds . standard 3.3v tri - state pwm mode if mode pin is grounded, the ir3548 accepts standard 3- level 3.3v pwm inp ut signals. as shown in figure 7, when pwm input is above v ih_ pwm , the synchronous mosfet is turned off and the control mosfet is turned on. when pwm input is below v il_ pwm , the control mosfet is turned off and synchronous mosfet is turned on. if pwm pin is floated, the built - in resistors pull the pwm pin into a tri - state region centered around 1.6v. ir active tri - level (atl) pwm inpu t signal when mode pin is tied to vcc, t he ir3548 gate drivers are driven by a patented tri - level pwm control signal provided by the ir digital pwm controllers. during normal operation, the rising and falling edges of the pwm signal transition between 0v and 1.8v to control pulse width modulation of the integrated mosfets. to force both mosfets off s imultaneously, the pwm signal crosses a tri - state voltage level higher than the v th _atl tri - state threshold. this threshold based tri - state results in a very fast disable for both the mosfet pairs with only a small tri - state propagation delay. mosfet switching resumes when the pwm signal falls below the v tl_atl tri - state threshold into the normal operating voltage range. figures 8 s how s the pwm input and the corresponding sw and gatel output of the ir3548. this fast tri - state operation eliminates the need for any tri - state hold - off time of the pwm signal to dwell in the shutdown w indow. dedicated disable or enable pins are not required which simplifies the routing and layout in applications with a limited number of board layers. it also provides the
ir3548 20 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 switching free of shoot - through for slow pwm transition times of up to 20ns. the ir 3548 is therefore tolerant of stray capacitance on the pwm signal lines. the ir3548 provides a pull - up bias current to drive the pwm input to the tri - state condition of 3.3v when the pwm controller output is in its high impedance state. multi - level pull - up currents are designed to drive worst case stray capacitances and allows for pwm transition s into the tri - state condition rapidly to avoid a prolonged period of mosfet conduction during faults. the pull - up currents are disabled once the pwm pin exceeds the tri - state threshold to conserve power. dual, double r or quad driver mode selection the function pin is used to select t hree different operating driver modes , dual driver, doubler driver and quad driver so that one pwm can control one - , two - or four - phase buck converter . as shown in table 1, connecting function to lgnd sets dual driver mode while tying function pin to vcc selects doubler mode. leaving function pin float sets quad driver mode. these p hase modes are shown in figure s 3 to 6 and figure s 9 to 11 . detailed timing d iagrams for ir atl mode can be seen in figure s 9 to 11 . in dual driver mode, two independent pwm signals control two respective phases with separate enable control . this mode is primarily used in a two - phase converter with a two - phase pw m controller , as shown in figure 3 and figure 9. it can also be used in single - phase operation as shown in figure 5 or in converters with two independent output rails, as shown in figure 4 . in doubler driver mode, a single input signal at pwm1 controls two phases , where phase 1 follows pwm1 signal and phase 2 is 180 phase behind the pwm1 signal . the current signal of the two phases should be summed and then connected to the pwm controller, as shown in figure 6 and figure 10. in quad driver mode, two ir3548 devices are used with one configured as a master and one as a sl ave , as shown in figure 11 . one pwm signal at pwm1 controls four phases with the sequence of phase 1 of the master ir3548 , phase 1 of the s lave ir3548 , phase 2 of master ir3548, and phase 2 o f s lave ir3548. the phase delay is 90 between the phases. the current signal of the four phases should be summed and then connected to the pwm controller. enable control there are two enable inputs in the ir3548, en1 and en2. in dual mode, each phase has i t s own enable input . respective control and synchronous mosfets are held off while en1 and en2 are low. if only one phase operation is desired, the en2 pin must be grounded. in doubler and quad modes, only en1 is available. en1 low places both phases in high impedance by turning off all four mosfets. internal blocks are shut down to reduce vcc and vdrv quiescent currents to 1ua (typical) when both phases are turned off. the vin 1 input voltage sense resistor divider (vindiv) is also disconnected when en1 is low to further reduce bias currents. the ir3548 is ready to accept pwm activity in less than 10 us af ter the part is enabled via en1 , as shown in figure 31. integrated bootstrap pfet the ir3548 features an integrated bootstrap pfet per phase to reduce ext ernal component count. this enables the ir3548 to be used effectively in cost and space sensitive designs. the bootstrap circuit is used to establish the control mosfet gate driver bias voltage and consists of a pfet and an external capacitor connected bet ween the sw and boot pins of each phase. the external bootstrap capacitor is charged through the pfet when the respective sw node is low . control mosfet driver each control mosfet driver is able to drive a n- channel mosfet at frequency up to 1 .5 mhz. the ex ternal bootstrap boot pin capacitor referenced to the sw node is used to bias the in ternal mosfet gate. when the sw node is at ground, the boot strap capacitor is charged to the vdrv supply voltage using the boot pfet and this stored charge is used to bias the internal mosfet when the pwm signal goes high. once the control mosfet is
ir3548 21 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 turned on, the sw voltage is driven to the vin supply voltage and the boot pin voltage is equal to vin plus the vdrv voltage without any bootstrap diode voltage drop . when the pw m signal goes low, the control mosfet is turned off by pulling the gate to the sw voltage. synchronous mosfet driver the ir3548 synchronous mosfet driver is designed to drive the internal n - channel mosfet to frequencies of 1 .5 mhz. the driver is biased from the vdrv supply voltage to turn the mosfet on . when the synchronous mosfet is turned on the sw node is pulled to ground. this allows re charging of the boot strap capacitor for the next synchronous mosfet drive event . adaptive dead time a djustment in a synchronous buck c onverter care should be taken to prevent both control and synchronous mosfets from being on simultaneously. such an event could result in very large shoo t- through currents and lead to long term degradation of the power stage. a fixed dead time does not provide optimal performance due to variations in converter duty cycles , bias voltages and temperature . the ir3548 provides an adaptive dead time adjustment to minimize dead time to an optimum duration which allows for maximum efficiency. the ?break before make? adaptive design is achieved by monitoring gate and sw voltages to determine the on or off status of a mosfet. adaptive dead time also provides zero - voltage switching (zvs) of the synchronous mosfet with minimum curr ent conduction through its body diode. during normal operation the pwm transitions between low and high voltage levels to drive the control and synchronous mosfets. the high voltage level is 1.8v for ir atl mode and 3.3v for standard pwm mode. the pwm signal falling edge transition to a low voltage threshold initiates the control mosfet driver turn off after a short propagation delay. the dead time control circuit monitors the internal high gate signals and respective sw voltages to ensure the control mosfet is turned off before turning on the synchronous mosfet. the pwm rising edge transition to a high voltage threshol d initiates the turn off of the synchronous mosfet after a small propagation delay. the adaptive dead time circuit provides the appropriate dead tim e by determi ning if the synchronous mosfet gate voltage has cross ed the lower threshold before allowing the turn on of the control mosfet. input voltage divide r the vindiv can be used to provide input voltage vin1 information to the pwm controller with a ratio of 1/14 through an internal resistor divider, which is disconnected from vin1 when en1 is low to reduce the bias current of the ir3548. frequency range the ir3548 is designed to operate over a wide frequency range. when operating in dual mode, the pwm input and respective sw out put frequencies are identical. when operating in doubler mode, the pwm1 input frequency is twice the sw1 or sw2 output frequencies . when operating in quad mode, the master pwm1 input frequency is four times the four sw output frequenc ies . the lower limit of the output frequency range is dictated by the size of the boot capacitor which provide s bias to the control mosfet driver during the entire on - time. the upper limit of frequency is determined by thermal limitations as well as pulse wid th limitations. the ir3548 is designed to operate with switching frequencies of each phase between 20 0khz and 1 .5 mhz . using a dual mode dr iver as a single driver to use the ir3548 in a single phase converter, simply set dual mode, ground en2 pin and leave the unused pwm 2 input floating, as shown in figure 5. dual mode reaction t o tri - state pwm input anytime there is a tri - state on the pwm1 or pwm2 , the respective sw output is tri - stated.
ir3548 22 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 doubler/quad mode reaction to tri - state pwm input in dual and quad mode, anytime there is a tri - state on the master pwm1, all outputs (sw1 and sw2 ) are tri - stated. when the pwm1 transitions from a tri - state to a high and then from a high to a low, only phase 1 (sw1) operates. this allows the vr to operate properly in ps2 m ode and during load releases. in quad mode, both pwmio 1 and pwmio2 signals of the master ir3548 go to 5v when pwm 1 is tri - state to force the slave ir3548 to keep both control and synchronous mosfets off. once the pwm1 sees a transition from a low to a high (absence of tri - state) , the driver leaves single phase operation and returns to the doubler or q uad functionality , as shown in figure 10 and figure 11 . application informat ion configuring the pwm and phase modes the ir3548 can operate in 3 different pwm input modes including dual, doubler and quad modes (master and slave). dual and doubler modes can accept either a n ir atl input pwm signal or a tri - state pwm signal (3.3v or 5v) while quad mode can only accept atl mode since pwm tri - state transition delays can not be tolerated when the pwm needs to operate at 4 times the swit ch ing frequency. table 1 on page 3 shows the configuration of both the pwm mode s and the driver m odes utiliz ing the function and mode pins. note that depending on the mode selected in table 1, pin 14 (pwm2 / pwmio1) and pin 15 (en2 / pwmio2) change f unction s as well. the function and mode selection pins are latched into the ir3548 at power up and during en1 cycling , and cannot be changed after these events. power loss calculati on the t wo - phase ir3548 efficiency and power loss measureme nt circuit is shown in figure 3 4 . the ir3548 power loss is determined by, vdrv drv vcc cc in in loss ivivivp ++= 2/) ( 21 out sw sw ivv +? where both mosfet loss and the driver loss are included, but the pwm controller and the inductor losses are not included. figure 34: ir3548 power loss measurement figure 1 2 shows the measured two - phase ir3548 efficiency under the default test conditions, v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh ( 0.2 9m dual driver mode, vdrv = 7v, t ambient = 25c , no heat sink, and no air flow. the measured two - phase ir3548 power loss under the same con ditions is provided in figure 1 3 . if any of the application condition s , i.e. input voltage, output voltage, switching frequency, vcc mosfet driver voltage or inductance, is d ifferent from those of figure 1 3 , a set of normalized power loss curves should be used. obtain the normalizing factors from figure 14 to figure 18 for the new application conditions; multiply these factors by the powe r loss obtained from figure 13 for the required load current. as an example, the power loss calculation procedures under different conditions, v in =10v, v out =1v, ? sw = 300khz, l=210 nh , vcc= 5v, vdrv = 5v, i out =50a, t ambient = 25c , no heat s ink, and no air flow, are as follows.
ir3548 23 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 1) determine the power loss at 50a under the default test conditions of v in =12v, v out =1.2v, ? sw = 400khz, l=150 nh , vcc = 5v, vdrv = 7v, t ambient = 25c , no heat sink, and no air flow. it is 5.5w from figure 1 3. 2) determine the input voltage normalizing factor with v in =10v, which is 0.96 based on the dashed lines in figure 1 4. 3) determine the output voltage normalizing factor with v out =1v, which is 0.94 based on the dashed lines in figure 15. 4) determine the switching frequency norma lizing factor with ? sw = 300khz, which is 0.99 based on the dashed lines in figure 16. 5) determine the vdrv mosfet drive voltage normalizing factor with v drv = 5v, which is 1. 25 based on the dashed lines in figure 17. 6) determine the inductance normalizing facto r with l=210 nh , which is 0.95 based on the dashed lines in figure 18 . 7) multiply the power loss under the default conditions by the five normalizing factors to obtain the power loss under the new conditions, which is 5.5 w x 0.96 x 0.94 x 0.99 x 1.25 x 0.95 = 5.83 w. thermal derating figure 19 shows the ir3548 thermal derating curve with t he case temperature controlled at or below 125c. the test conditions are v in =12v, v out =1.2v, ? sw =400khz, l=150 nh ( 0.2 9m ), vdrv=7v, t ambient = 0 c to 100 c , no heat sink, an d airflow = 0lfm / 100lfm / 200lfm / 400lfm. if any of the application condition, i.e. input voltage, output voltage, switching frequency, vdrv mosfet driver voltage, or inductance is different from those of figure 19, a set of ir35 4 8 case temperature adju stment curves should be used. obtain the te mperature deltas from figure 1 4 to figure 18 for the new application conditions; sum these deltas and then subtract from the ir3548 case tem perature obtained from figure 19 for the required load current. the ir3548 safe operating area is obtained with the case temperature controlled at or below 125c. if a lower case temperature is desired, reduce the highest ambient temperature by the same delta. as an example, the highest ambient temperature calculation procedures for a different operating condition, v in =10v, v out =1v, ? sw = 300khz, l=210 nh , vdrv = 5v, i out =50a, t ambient = 25c , no heat sink, and no air flow, are as follows. 8) from figure 19 , determine the highest ambient temperature at the required load current unde r the default conditions, which is 59 c at 50a with 0lfm airflow and the ir3548 case temperature of 125c. 9) determine the case temperature with v in =10v, which is - 1.0 based on the dashed lines in figure 1 4. 10) determine the case temperature with v out =1v, whi c h is - 1.4 based on the dashed lines in figure 1 5. 11) determine the case temperature with ? sw = 300khz, which is - 0.2 based on the dashed lines in figure 1 6. 12) determine the case temperatu re with vdrv = 5v, which is + 5.5 based on the dashed lines in figure 1 7. 13) determine the case tempera ture with l=210nh, which is - 1.1 based on the dashed lines in figure 18 . 14) sum the case temperature adjustment from 9) to 13), - 1.0 - 1.4 - 0.2 + 5.5 - 1.1 = + 1.8 . deduct the delta from the highest ambient temperature in ste p 8), 59c - (+ 1.8 c) = 57 .2 c. 15) if the desired ir3548 case temperature is 105c instead of 125c, subtract 20c ( =125c - 105c) from the highest ambient temperature obtained from 14), i.e. 57.2c - 20c = 37 .2 c. input capacitors c vin at least one 10uf 1206 ceramic capacitors and one 0.1uf 0402 ceramic capacitor are recommended for decoupling the vin 1 and vin2 to pgnd connection . the 0.1uf 0402 capacitor should be on the same
ir3548 24 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 side of the pcb as the ir3548 and next to the vin1/vin2 and pgnd pins. adding a dditional capacitance and use of capacitors with lower esr and mounted with low inductance routing will improve efficiency and reduce overall system noise, especially in single - phase designs or during high current operation. bootstrap capacitor s c boot 1 and c boot2 a minimum of 0.22uf 0402 capacitor is required for the bootstrap circuit. it should be mounted on the same side of the pcb as the ir3548 and as close as possible to the boot1 / boot2 pin. a low inductance routing of the sw1 / sw2 pin connection to the other terminal of the bootstrap capacitor is strongly recommended. vcc and vdrv decoupling c apacitor s c vcc and c vdrv a 0.1uf ceramic decoupling capacitor is required at the vcc pin. a 1uf ceramic decoupli ng capacitor is required at the vdrv pin. they should be mounted on the same side of the pcb as the ir3548. the vcc capacitor should be as close as possible to the vcc and lgnd. the vdrv capacitor should be as close as possible to hvcc/lvcc and pgnd (pin 10). low inductance routing for the decoupling c apacitors is strongly recommended. pcb layout c onsiderations pcb layout and design is important to driver performance in voltage regulator circuits due to the high current slew rate (di/dt) during mosfet switching. contact international rectifier for a lay out example suitable for your specific application. ? locate all power components in each phase as close to each other as practically possible in order to minimize parasitics and losses, allowing for reasonable airflow. ? input supply decoupling and bootstrap capacitors should be physically located close to their respective ic pins. ? gatel1 and gatel2 interconnect trace inductances should be minimized to prevent cdv/dt turn - on of the low side mosfet s. ? the ground connection of the ic should be as close as possibl e to the low - side mosfet source. ? use of a copper plane under and around the ic and thermal vias to connect to buried copper layers improves the thermal performance substantially.
ir3548 25 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 metal and component placement ? lead land width should be equal to nominal p art lead width. the minimum lead to lead vsdflqjvkrxogeh?ppwrsuhyhqw shorting. ? lead land length should be equal to maximum part lead length +0.15 - 0.3 mm outboard extension and 0 to + 0.05mm inboard extension. the outboard extension ensures a large and visible toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. ? only 0.30mm diameter via shall be placed in the area of the power pad lands and connected to power planes to minimize the noise effect on the ic and to improve thermal performance.
ir3548 26 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resi st miss - alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure s nsmd pads. ? the minimum solder resist width is 0.13mm typical. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a so lder uhvlvwzlgwkri?ppuhpdlqv ? the power land pads vin, pgnd, and sw should be solder mask defined (smd). ? ensure that the solder resist in - between the ohdgodqgvdqgwkhsdgodqglv?ppgxh to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. figure 35: solder resist
ir3548 27 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 stencil design ? the stencil apertures for the lead lands should be approximately 65% to 75% of the area of the lead lands depending on stencil thickness. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable s older release. ? the low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. ? the power pads vin, pgnd and sw, land pad apertures should be approximately 65% to 75% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. solder paste on large pads is broken down into small sections with a minimum gap of 0.2mm between allowing for out - ga ssing during solder reflow. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. figure 36: stencil design * contact international rectifier to receive an electronic pcb library file in cadence allegro or cad dxf/dwg format.
ir3548 28 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 marking information 3548m ? yww ? xxxxx site / date / marking code lot code figure 37 : pqfn 6mm x 8mm
ir3548 29 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 package information figure 38 : pqfn 6mm x 8mm
30 www.irf.com ? 20 14 i nternational rectifier submit datasheet feedback january 08, 2014 data and specifications subject to change without notice. this product will be designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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